During the course of normal operation, a processor and/or portions thereof may spend a significant amount of time waiting for input without performing any other tasks. For example, during execution of instructions a processing unit may execute a halt instruction. In this circumstance the processor may wait for an interrupt or other event prior to continuing with execution. Such events may include elapsed timer indications and input/output (IO) events, or other indications that data is ready. In a basic halt scenario, the processor may simply wait for the event while maintaining power to all of its circuitry.
Because the processor cannot perform such execution tasks while halted apart from waiting and maintaining validity of registers or other volatile data stores, a net savings in power may be achieved under certain circumstances by powering down the processor or parts of the processor during such times.